The present invention relates to data processing systems, and more particularly, the memories used in data processing systems.
During the operation of a data processing system, it is frequently necessary for data stored in the memory of the data processing system to be changed or updated. It is normally desired that any data changes be made as quickly as possible, since data updated during one step of a computer program may be needed during a subsequent program step.
In the past, it has not been difficult for data stored in a memory to be updated, since it was largely a matter of writing the new or updated data directly into the memory at the location of the old data. Where individual bits within a data word or group of bits stored at a memory location were to be changed, either a complete data word having the new data bits was generated or the memory was so constructed that each bit within the data word could be separately accessed and changed.
Permitting a memory to be written into at each individual bit location, however, tends to decrease the speed with which the memory can be accessed, since additional memory addresses are required for addressing individual bits. The resulting loss of speed in unacceptable in small, fast access memories, such as the scratch pad memory commonly used within the processor of a data processing system. If an individual bit is to be changed in such memories as presently designed, it is necessary that the entire data word containing the bit be read out of the memory, that the new bit be inserted into the word, and that the entire data word be written back into the original memory location. Using this approach, however, also decreases the speed of such memories since the memory is tied up during the reading and writing of the data word and is incapable of being accessed for other operations.
The use of duplicate memories, where each of two memories stores identical data, has been proposed in the past. For example, in U.S. Pat. No. 4,135,242, issued to William P. Ward et al. and assigned to the same assignee as the present application, there is shown in a processor a dual port scratch pad memory comprised of two memories containing duplicate data. During the operation of the processor, both memories can be accessed for operands. If an operation is to be carried out requiring two operands, both operands are fetched simultaneously.
Despite the use of duplicate memories in the past, there has not been provided a way to change individual bits in a word-addressable memory and, during the clock cycle that the bit is being changed, leave the memory in a condition so that it may be accessed during the same cycle for purposes of obtaining an operand or operands in carrying out some other processor operation.